In recent months, ARTEMIS has turned its attention to just some of the projects orchestrated by our 200 members within ECSEL JU. From nano-sized chips to advanced cyber-physical systems (CPS), these often pave the way for major technological shifts in Europe and beyond, for which they certainly deserve greater recognition.
“The advent of advanced CPS requires high-performance requirements to cope with the newest functionalities,” explains Eduardo Quiñones, Senior Researcher at Barcelona Supercomputing Center. “AMPERE therefore aims to provide the foundations for future CPS which are capable of exploiting the performance capabilities of the most advanced processor architectures featuring acceleration devices while maintaining the benefits of model-driven engineering.”
As the project coordinator, Eduardo works with nine diverse partners in seven European countries on the goal of accounting for non-functional requirements inherited from cyber-physical interactions, such as time predictability, energy efficiency, safety and security. Thanks to a budget of almost five million euros and the involvement of huge players like Bosch and Thales, AMPERE will ultimately demonstrate its novel technology through two real-world use-cases in the automotive and railway domains.
“AMPERE is promoting the introduction of parallel programming models currently used in supercomputers in order to provide the right level of performance,” Eduardo continues. “This means developing a software framework for the design, development and execution of advanced CPS, addressing the complete system stack from the application design with model-based engineering to an automatic transformation of the underlying parallel programming model, the analysis of the non-functional requirements and support for the operating system and hypervisor.”
To achieve this, the project aims to bridge the gap between the model-driven engineering used in CPS and the parallel programming models used in high-performance computing – a crucial technical challenge in both the system design and the computing software stack of CPS. However, the rewards are rich: by targeting the most advanced energy-efficient and highly-parallel heterogeneous platforms, full exploitation of performance-demanding emerging technologies like artificial intelligence and big data analytics should be possible.
Having begun in January 2020, AMPERE is now roughly halfway towards completion. In addition to his technological focus, Eduardo is working hard to raise awareness of the project, including an appearance on the Embedded Executives podcast and a guest blog on Embedded Computing Design – the largest electronics engineering community across digital, print and live event platforms. “Moreover, AMPERE is in contact with the committees of some of the programming languages used in both computing domains (e.g. OpenMP and Ada) to reconciliate the requirements needed in the two domains,” he adds. This will maximise performance while fulfilling non-functional requirements, ensuring a strong impact for the foreseeable future.
As for a model of such long-term success, SeNaTe provides a golden example. Through the combined efforts of 40 partners and a budget of almost 178 million euros, this project oversaw the key aspects of the R&D needed to enable the production of the first commercial 7-nanometre node chips using extreme ultraviolet (EUV) lithography tools, as well as over 50 publications and 33 patents. Following its completion in March 2018, devices based on this technology node were introduced to the market in several smartphones announced in late 2019 (such as the Huawei Kirin and Samsung Exynos).
“The SeNaTe project was part of a chain of thematically-connected initiatives to advance semiconductor technology solutions under ECSEL,” notes Arco Krijgsman, Project Manager Public Private Partnerships at coordinating partner ASML. “Its key success lay in the fact that it fostered close collaboration between equipment suppliers in lithography, metrology and processing equipment to research and technology organisations. The project resulted in the validation of equipment and process technology solutions on Imec’s ‘pilot line’, meeting the specifications for the 7-nm node.”
This node forms the latest advancement in commercial chip technology, enabling faster and more energy-efficient processors through its smaller feature size and transistors. In turn, this translates into wider functionalities and less power consumption for smartphones and other electronic devices. As Arco points out, this was a vital step towards unlocking even greater potential. “The solutions developed in SeNaTe also formed the basis for developments in subsequent technology nodes. There are the TAKE5 and TAKEMI5 projects (in which the innovations were extended to create 5-nm technology) and IT2 and ID2PPAC that will be looking into developing solutions for the 2-nm technology node, the latter of which is to start in June this year.”
In addition to metrology and lithography, SeNaTe required breakthroughs in materials for masks and chips and process integration. Using ultraviolet wavelengths of just 13.5 nanometres, the resulting technology is able to transfer a pattern from a photomask to a light-sensitive material on the integrated circuit, thereby guiding the deposition process to print the integrated circuit. Subsequent uptake within the electronics industry helped keep Moore’s Law alive despite some doubts in the early 2010s.
“SeNaTe has been part of a successful chain of ‘More Moore’ thematic projects that have been running with EU support since the late 1990s,” concludes Arco. “The project activities are continuing through ongoing public-private initiatives and are all aimed at driving the migration to successive chip technology nodes. As such, these projects will continue to significantly contribute to the expansion and prosperity of European industries for semiconductor manufacturing tools, the chip industry and related sectors for decades to come, fuelling innovation and patent registrations as well as revenue and jobs growth.”